Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

8.2. Generation of Avalon-MM Interrupts

The generation of Avalon-MM interrupts requires the instantiation of the CRA slave module where the interrupt registers and control logic are implemented. The CRA slave port has an Avalon-MM Interrupt output signal, cra_Irq_irq. A write access to an Avalon-MM mailbox register sets one of the P2A_MAILBOX_INT<n> bits in the Avalon-MM to PCI Express Interrupt Status Register and asserts the cra_Irq_o or cra_Irq_irq output, if enabled. Software can enable the interrupt by writing to the INT_X Interrupt Enable Register for Endpoints through the CRA slave. After servicing the interrupt, software must clear the appropriate serviced interrupt status bit in the PCI‑Express‑to-Avalon-MM Interrupt Status register and ensure that no other interrupt is pending.