Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

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ID 683724
Date 9/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Parameter Settings 4. Physical Layout 5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 6. Registers 7. Reset and Clocks 8. Interrupts for Endpoints 9. Error Handling 10. Design Implementation 11. Throughput Optimization 12. Additional Features 13. Avalon-MM Testbench and Design Example 14. Avalon-MM Testbench and Design Example for Root Port 15. Hard IP Reconfiguration 16. Debugging A. PCI Express Protocol Stack B. Transaction Layer Packet (TLP) Header Formats C. Lane Initialization and Reversal D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive E. Document Revision History
1. Datasheet x
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components for the Avalon® -MM Endpoint 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Parameter Settings x
3.1. Parameters 3.2. Avalon-MM Settings 3.3. Base Address Register (BAR) Settings 3.4. Device Identification Registers 3.5. PCI Express and PCI Capabilities Parameters 3.6. Configuration, Debug, and Extension Options 3.7. Vendor Specific Extended Capability (VSEC) 3.8. PHY Characteristics 3.9. Example Designs
3.5. PCI Express and PCI Capabilities Parameters x
3.5.1. Device Capabilities 3.5.2. Error Reporting 3.5.3. Link Capabilities 3.5.4. MSI and MSI-X Capabilities 3.5.5. Slot Capabilities 3.5.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
5.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 5.2. Bursting and Non-Bursting Avalon® -MM Module Signals 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 5.4. Clock Signals 5.5. Reset, Status, and Link Training Signals 5.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 5.7. Hard IP Status Signals 5.8. Physical Layer Interface Signals
5.7. Hard IP Status Signals x
5.7.1. Hard IP Reconfiguration Interface
5.8. Physical Layer Interface Signals x
5.8.1. Serial Data Signals 5.8.2. PIPE Interface Signals 5.8.3. Arria® 10 Development Kit Conduit Interface 5.8.4. Test Signals
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 6.8. Programming Model for Avalon-MM Root Port 6.9. Uncorrectable Internal Error Mask Register 6.10. Uncorrectable Internal Error Status Register 6.11. Correctable Internal Error Mask Register 6.12. Correctable Internal Error Status Register
6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
6.7.1. Avalon-MM to PCI Express Interrupt Registers
6.7.1. Avalon-MM to PCI Express Interrupt Registers x
6.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 6.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 6.7.1.3. PCI Express Mailbox Registers 6.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 6.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 6.7.1.6. Avalon-MM Mailbox Registers 6.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
6.8. Programming Model for Avalon-MM Root Port x
6.8.1. Sending a Write TLP 6.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 6.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 6.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 6.8.5. Root Port TLP Data Registers
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Clocks
7.2. Clocks x
7.2.1. Clock Domains 7.2.2. Clock Summary
7.2.1. Clock Domains x
7.2.1.1. coreclkout_hip 7.2.1.2. pld_clk
8. Interrupts for Endpoints x
8.1. Enabling MSI or Legacy Interrupts 8.2. Generation of Avalon-MM Interrupts 8.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. Design Implementation x
10.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.2. Recommended Reset Sequence to Avoid Link Training Issues 10.3. SDC Timing Constraints
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
13. Avalon-MM Testbench and Design Example x
13.1. Avalon-MM Endpoint Testbench 13.2. Endpoint Design Example 13.3. Avalon-MM Test Driver Module 13.4. Root Port BFM 13.5. BFM Procedures and Functions 13.6. Setting Up Simulation
13.2. Endpoint Design Example x
13.2.1. BAR/Address Map 13.2.2. BAR Setup
13.4. Root Port BFM x
13.4.1. Root Port BFM Overview 13.4.2. Issuing Read and Write Transactions to the Application Layer 13.4.3. Configuration of Root Port and Endpoint 13.4.4. Configuration Space Bus and Device Numbering 13.4.5. BFM Memory Map
13.5. BFM Procedures and Functions x
13.5.1. ebfm_barwr Procedure 13.5.2. ebfm_barwr_imm Procedure 13.5.3. ebfm_barrd_wait Procedure 13.5.4. ebfm_barrd_nowt Procedure 13.5.5. ebfm_cfgwr_imm_wait Procedure 13.5.6. ebfm_cfgwr_imm_nowt Procedure 13.5.7. ebfm_cfgrd_wait Procedure 13.5.8. ebfm_cfgrd_nowt Procedure 13.5.9. BFM Configuration Procedures 13.5.10. BFM Shared Memory Access Procedures 13.5.11. BFM Log and Message Procedures 13.5.12. Verilog HDL Formatting Functions
13.5.9. BFM Configuration Procedures x
13.5.9.1. ebfm_cfg_rp_ep Procedure 13.5.9.2. ebfm_cfg_decode_bar Procedure
13.5.10. BFM Shared Memory Access Procedures x
13.5.10.1. Shared Memory Constants 13.5.10.2. shmem_write Task 13.5.10.3. shmem_read Function 13.5.10.4. shmem_display Verilog HDL Function 13.5.10.5. shmem_fill Procedure 13.5.10.6. shmem_chk_ok Function
13.5.11. BFM Log and Message Procedures x
13.5.11.1. ebfm_display Verilog HDL Function 13.5.11.2. ebfm_log_stop_sim Verilog HDL Function 13.5.11.3. ebfm_log_set_suppressed_msg_mask Task 13.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 13.5.11.5. ebfm_log_open Verilog HDL Function 13.5.11.6. ebfm_log_close Verilog HDL Function
13.5.12. Verilog HDL Formatting Functions x
13.5.12.1. himage1 13.5.12.2. himage2 13.5.12.3. himage4 13.5.12.4. himage8 13.5.12.5. himage16 13.5.12.6. dimage1 13.5.12.7. dimage2 13.5.12.8. dimage3 13.5.12.9. dimage4 13.5.12.10. dimage5 13.5.12.11. dimage6 13.5.12.12. dimage7
13.6. Setting Up Simulation x
13.6.1. Using the PIPE Interface for Gen1 and Gen2 Variants 13.6.2. Viewing the Important PIPE Interface Signals 13.6.3. Disabling the Scrambler for Gen1 and Gen2 Simulations 13.6.4. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
14. Avalon-MM Testbench and Design Example for Root Port x
14.1. Overview of the Design Example 14.2. Overview of the Simulation Testbench
14.1. Overview of the Design Example x
14.1.1. Example Design Generation 14.1.2. Directory Structure for the Generated Design Example
14.2. Overview of the Simulation Testbench x
14.2.1. Simulating the Design Example
15. Hard IP Reconfiguration x
15.1. Reconfigurable Read-Only Registers in the Hard IP for PCI Express
16. Debugging x
16.1. Simulation Fails To Progress Beyond Polling.Active State 16.2. Hardware Bring-Up Issues 16.3. Link Training 16.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 16.5. Use Third-Party PCIe Analyzer 16.6. BIOS Enumeration Issues
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Interrupts A.1.4. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block A.5.5. Preliminary Support for Root Port
B. Transaction Layer Packet (TLP) Header Formats x
B.1. TLP Packet Formats without Data Payload B.2. TLP Packet Formats with Data Payload
E. Document Revision History x
E.1. Document Revision History for the Arria® 10 and Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Parameter Settings
4. Physical Layout
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
6. Registers
7. Reset and Clocks
8. Interrupts for Endpoints
9. Error Handling
10. Design Implementation
11. Throughput Optimization
12. Additional Features
13. Avalon-MM Testbench and Design Example
14. Avalon-MM Testbench and Design Example for Root Port
15. Hard IP Reconfiguration
16. Debugging
A. PCI Express Protocol Stack
B. Transaction Layer Packet (TLP) Header Formats
C. Lane Initialization and Reversal
D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive
E. Document Revision History

15.1. Reconfigurable Read-Only Registers in the Hard IP for PCI Express

The following table lists all of the registers that you can update using the PCI Express reconfiguration block interface.

Table 82.  
Address Bits Description Default Value
0x00 0

When 0, PCIe reconfig mode is enabled. When 1, PCIe reconfig mode is disabled and the original read-only register values set in the programming file used to configure the device are restored.

b'1
0x01 - 0x88 -- Reserved. --
0x89 15:0 Vendor ID. 0x1172
0x8A 15:0 Device ID. 0x0001
0x8B 7:0 Revision ID. 0x01
0x8C 15:0 Class code[23:8]. --
0x8D 15:0 Subsystem vendor ID. 0x1172
0x8E 15:0 Subsystem device ID. 0x0001
0x8F -- Reserved. --
0x90 0 Advanced Error Reporting. b'0
3:1 Low Priority VC (LPVC). b'000
7:4 VC arbitration capabilities. b'0001
15:8 Reject Snoop Transaction. b'00000000
0x91 2:0
Max payload size supported. The following are the defined encodings:
  • 000: 128 bytes max payload size
  • 001: 256 bytes max payload size
  • 010: 512 bytes max payload size
  • 011: 1024 bytes max payload size
  • 100: 2048 bytes max payload size
  • 101: 4096 bytes max payload size
  • 110: Reserved
  • 111: Reserved
 b'010
3

Surprise Down error reporting capabilities. (Available in PCI Express Base Specification Revision 1.1 compliant Cores only).

Downstream Port. This bit must be set to 1 if the component supports the optional capability of detecting and reporting a Surprise Down error condition.

Upstream Port. For upstream ports and components that do not support this optional capability, this bit must be hardwired to 0. (Available in PCI Express Base Specification Revision 1.1 compliant Cores only).

b'0
4 (Available in PCI Express Base Specification Revision 1.1 compliant Cores only).

Downstream Port: This bit must be set to 1 if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management state machine.

Upstream Port: For upstream ports and components that do not support this optional capability, this bit must be hardwired to 0.

b'0
5 Extended TAG field supported b'0
8:6
Endpoint L0s acceptable latency. The following encodings are defined:
  • b'000 - Maximum of 64 ns
  • b'001 - Maximum of 128 ns
  • b'010 - Maximum of 256 ns
  • b'011 - Maximum of 512 ns
  • b'100 - Maximum of 1 μs
  • b'101 - Maximum of 2 μs
  • b'110 - Maximum of 4 μs
  • b'111- No limit
 b'000
11:9
Endpoint L1 acceptable latency. The following encodings are defined:
  • b'000 - Maximum of 1 μs
  • b'001 - Maximum of 2 μs
  • b'010 - Maximum of 4 μs
  • b'011 - Maximum of 8 μs
  • b'100 - Maximum of 16 μs
  • b'101 - Maximum of 32 μs
  • b'110 - Maximum of 64 μs
  • b'111 - No limit
 b'000
14:12
These bits record the presence or absence of the attention and power b'1 indicators.
  • [0]: Attention button present on the device.
  • [1]: Attention indicator present for an endpoint.
  • [2]: Power indicator present for an endpoint.
 b'1
15 Role-Based error reporting. (Available in PCI Express Base Specification Revision 1.1 compliant Cores only). --
0x92 1:0 Slot Power Limit Scale b'00
7:2 Max Link Width b'000100
9:8 L0s Active State power management support. L1 Active State power management support. b'01
15:10
L1 exit latency common clock. L1 exit latency separated clock. The following encodings are defined:
  • b'000 - Less than 1 µs
  • b'001 - 1 µs to less than 2 µs
  • b'010 - 2 µs to less than 4 µs
  • b'011 - 4 µs to less than 8 µs
  • b'100 - 8 µs to less than 16 µs
  • b'101 - 16 µs to less than 32 µs
  • b'110 - 32 µs to 64 µs
  • b'111 - More than 64 µs
 b'000000
0x93 0 Attention button implemented on the chassis. b'0000000
1 Power controller present.
2 Manually Operated Retention Latch (MRL) sensor present.
3 Attention indicator present for a root port, switch, or bridge.
4 Power indicator present for a root port, switch, or bridge.
5 Hot-plug surprise: When this bit set to1, a device can be removed from this slot without prior notification.
6 Hot-plug capable.
9:7 Reserved b'000
15:10 Slot Power Limit Value b'000000
0x94 1:0 Reserved --
2 Electromechanical Interlock present (Available in PCI Express Base Specification Revision 1.1 compliant Cores only). b'0
15:3 Physical Slot Number (if slot implemented). This signal indicates the physical slot number associated with this port. It must be unique within the fabric. b'0
0x95 7:0 NFTS_SEPCLK. The number of fast training sequences for the separate clock. b'10000000
15:8 NFTS_COMCLK. The number of fast training sequences for the common clock. b'10000000
0x96 3:0
Completion timeout ranges. The following encodings are defined:
  • b'0001: range A
  • b'0010: range B
  • b'0011: range A&B
  • b'0110: range B&C
  • b'0111: range A,B&C
  • b'1110: range B,C&D
  • b'1111: range A,B,C&D

All other values are reserved.

 b'0000
4 Completion Timeout supported. 0: completion timeout disable not supported. 1: completion timeout disable supported b'0
7:5 Reserved b'000
8 ECRC generation b'0
9 ECRC checking b'0
10 No command completed support. (Available in PCI Express Base Specification Revision 1.1 compliant Cores only). b'0
13:11
Number of functions MSI-capable.
  • b'000: 1 MSI-capable
  • b'001: 2 MSI-capable
  • b'010: 4 MSI-capable
  • b'011: 8 MSI-capable
  • b'100: 16 MSI-capable
  • b'101: 32 MSI-capable
 b'010
14 MSI 32/64-bit addressing mode. b'0: 32 bits only. b'1: 32 or 64 bits. b'1
15 MSI per-bit vector masking (read-only field). b'0
0x97 0 Function supports MSI. b'1
3:1 Interrupt pins. b'001
5:4 Reserved b'00
6 Function supports MSI-X. b'0
15:7 MSI-X table size b'000000000
0x98 1:0 Reserved --
4:2 MSI-X Table BIR. b'000
15:5 MSI-X Table Offset. b'00000000000
0x99 15:10 MSI-X PBA Offset. b'000000
0x9A 15:0 Reserved 0x0000
0x9B 15:0 Reserved 0x0000
0x9C 15:0 Reserved 0x0000
0x9D 15:0 Reserved 0x0000
0x9E 3:0 Reserved --
7:4 Number of EIE symbols before NFTS. b'0100
15:8 Number of NFTS for separate clock in Gen2 rate. b'11111111
0x9F 7:0 Number of NFTS for common clock in Gen2 rate. b'11111111
8 Selectable de-emphasis. b'0
12:9
PCIe Capability Version.
  • b'0000: Core is compliant to PCIe Specification 1.0a or 1.1
  • b'0001: Core is compliant to PCIe Specification 1.0a or 1.1
  • b'0010: Core is compliant to PCIe Specification 2.0
  • b'0100: Core is compliant to PCIe Specification 3.0
b'0100
15:13
L0s exit latency for common clock.
  • Gen1: ( N_FTS (of separate clock) + 1 (for the SKIPOS) ) * 4 * 10 * UI (UI = 0.4 ns).
  • Gen2: [ ( N_FTS2 (of separate clock) + 1 (for the SKIPOS) ) * 4 + 8 (max number of received EIE) ] * 10 * UI (UI = 0.2 ns).
b'110
0xA0 2:0
L0s exit latency for separate clock.
  1. Gen1: ( N_FTS (of separate clock) + 1 (for the SKIPOS) ) * 4 * 10 * UI (UI = 0.4 ns).
  2. Gen2: [ ( N_FTS2 (of separate clock) + 1 (for the SKIPOS) ) * 4 + 8 (max number of received EIE) ] * 10 * UI (UI = 0.2 ns).
  • b'000 - Less than 64 ns
  • b'001 - 64 ns to less than 128 ns
  • b'010 - 128 ns to less than 256 ns
  • b'011 - 256 ns to less than 512 ns
  • b'100 - 512 ns to less than 1 µs
  • b'101 - 1 µs to less than 2 µs
  • b'110 - 2 µs to 4 µs
  • b'111 - More than 4 µs
 b'110
15:3 Reserved 0x0000
0xA1   BAR0[31:0]  
0 BAR0[0]: I/O Space b'0
2:1 BAR0[2:1]: Memory Space. The following encodings are defined:
  • 2'b10: 64-bit address
  • 2'b00: 32-bit address
 b'10
3 BAR0[3]: Prefetchable. b'1
  BAR0[31:4]: BAR size mask. 0xFFFFFFF
15:4 BAR0[15:4]. Bits [15:4] of BAR size mask. b'0
0xA2 15:0 BAR0[31:16]. Bits [31:16] of BAR size mask. b'0
0xA3   BAR1[63:32] b'0
0 BAR1[32]: I/O Space b'0
2:1 BAR1[34:33]: Memory Space (see bit settings for BAR0). b'0
3 BAR1[35]: Prefetchable. b'0
  BAR1[63:36]: BAR size mask b'0
15:4 BAR1[47:36]. Bits [47:36] of BAR size mask. b'0
0xA4 15:0 BAR1[63:48]. Bits [63:48] of BAR size mask. b'0
0xA5   BAR2[95:64] b'0
0 BAR2[64]: I/O Space b'0
2:1 BAR2[66:65]: Memory Space (see bit settings for BAR0). b'0
3 BAR2[67]: Prefetchable. b'0
  BAR2[95:68]: BAR size mask b'0
15:4 BAR2[79:68]. Bits [79:68] of BAR size mask. b'0
0xA6 15:0 BAR2[95:80]. Bits [95:80] of BAR size mask. b'0
0xA7   BAR3[127:96] b'0
0 BAR3[96]: I/O Space b'0
2:1 BAR3[98:97]: Memory Space (see bit settings for BAR0). b'0
3 BAR3[99]: Prefetchable. b'0
  BAR3[127:100]: BAR size mask b'0
15:4 BAR3[111:100]. Bits [111:100] of BAR size mask. b'0
0xA8 15:0 BAR3[127:112]: Bits [127:112] of BAR size mask. b'0
0xA9   BAR4[159:128] b'0
0 BAR4[128]: I/O Space b'0
2:1 BAR4[130:129]: Memory Space (see bit settings for BAR0). b'0
3 BAR4[131]: Prefetchable. b'0
  BAR4[159:132]: BAR size mask  
15:4 BAR4[143:132]. Bits [143:132] of BAR size mask. b'0
0xAA 15:0 BAR4[159:144]. Bits [159:144] of BAR size mask. b'0
0xAB   BAR5[191:160] b'0
0 BAR5[160]: I/O Space b'0
2:1 BAR5[162:161]: Memory Space (see bit settings for BAR0). b'0
3 BAR5[163]: Prefetchable. b'0
  BAR5[191:164]: Bar size mask. b'0
15:4 BAR5[175:164]. Bits [175:164] of BAR size mask. b'0
0xAC 15:0 BAR5[191:176]. Bits [191:176] of BAR size mask. b'0
0xAD 15:0 Expansion BAR[223:192]: Bar size mask. Expansion BAR[207:192]. b'0
0xAE 15:0 Expansion BAR[223:208]. b'0
0xAF 1:0
IO.
  • 00: no IO windows.
  • 01: IO 16-bit.
  • 10: prefetchable 64.
  • 11: IO 32-bit.
 b'0
3:2
Prefetchable.
  • 00: not implemented.
  • 01: prefetchable 32
  • 10: prefetchable 64
  • 11: 32 MSI capable
 b'0
15:4 Reserved --
0xB0 5:0 Reserved --
6
Selectable de-emphasis, operates as specified in the PCI Express Base Specification when operating at the 5.0GT/s rate:
  • 1: 3.5 dB
  • 0: -6 dB

This setting has no effect when operating at the 2.5GT/s rate.

  
9:7 Transmit Margin. Directly drives the transceiver tx_pipemargin bits.  
0xB1 - 0xFF -- Reserved  
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