Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents
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1.8. Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).

The Avalon-MM soft logic bridge operates as a front end to the hardened protocol stack. The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

Table 6.  Resource Utilization Avalon-MM Hard IP for PCI Express

Interface Width

ALMs

M20K Memory Blocks

Logic Registers

Avalon‑MM Bridge

64

1100

17

1500

128

1900

25

2900

Avalon-MM Interface–Completer Only

64

650

8

1000

128

1400

12

2400

Avalon-MM–Completer Only Single Dword

64

250

0

350