Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

15. Hard IP Reconfiguration

The Arria 10 Hard IP for PCI Express reconfiguration block allows you to dynamically change the value of configuration registers that are read-only. You access this block using its Avalon-MM slave interface. You must enable this optional functionality by turning on Enable Hard IP Reconfiguration in the GUI. For a complete description of the signals in this interface, refer to Hard IP Reconfiguration Interface.

The Hard IP reconfiguration block provides access to read-only configuration registers, including Configuration Space, Link Configuration, MSI and MSI-X capabilities, Power Management, and Advanced Error Reporting (AER). This interface does not support simulation.

The procedure to dynamically reprogram these registers includes the following three steps:
  1. Bring down the PCI Express link by asserting the hip_reconfig_rst_n reset signal, if the link is already up. (Reconfiguration can occur before the link has been established.)
  2. Reprogram configuration registers using the Avalon-MM slave Hard IP reconfiguration interface.
  3. Release the npor reset signal.
Note: You can use the LMI interface to change the values of configuration registers that are read/write at run time. For more information about the LMI interface, refer to LMI Signals.