Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

B.2. TLP Packet Formats with Data Payload

Figure 89. Memory Write Request, 32-Bit Addressing
Figure 90. Memory Write Request, 64-Bit Addressing
Figure 91. Configuration Write Request Root Port (Type 1)
Figure 92. I/O Write Request
Figure 93. Completion with Data
Figure 94. Completion Locked with Data
Figure 95. Message with Data