Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents
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1.5. Configurations

The Avalon-MM Intel® Arria® 10 Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:

  • Physical (PHY), including:
    • Physical Media Attachment (PMA)
    • Physical Coding Sublayer (PCS)
  • Media Access Control (MAC)
  • Data Link Layer (DL)
  • Transaction Layer (TL)

When configured as an Endpoint, the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI Express using the Avalon-MM supports memory read and write requests and completions with or without data.

Figure 2. PCI Express Application with a Single Root Port and EndpointThe following figure shows a PCI Express link between two Intel® Arria® 10 or Intel® Cyclone® 10 GX FPGAs.
Figure 3. PCI Express Application Using Configuration via Protocol The Intel® Arria® 10 design below includes the following components:
  • Two Endpoints that connect to a PCIe switch.
  • A host CPU that implements CvP using the PCI Express link connects through the switch.