Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 9/10/2024
Public
Document Table of Contents

13.2.1. BAR/Address Map

The design example maps received memory transactions to either the target memory block or the control register block based on which BAR the transaction matches. There are multiple BARs that map to each of these blocks to maximize interoperability with different variation files. The following table shows the mapping.

Table 77.   BAR Map

Memory BAR

Mapping

32-bit BAR0

32-bit BAR1

64-bit BAR1:0

Maps to 32 KB target memory block. Use the rc_slave module to bypass the chaining DMA.

32-bit BAR2

32-bit BAR3

64-bit BAR3:2

Maps to DMA Read and DMA write control and status registers, a minimum of 256 bytes.

32-bit BAR4

32-bit BAR5

64-bit BAR5:4

Maps to 32  KB target memory block. Use the rc_slave module to bypass the chaining DMA.

Expansion ROM BAR

Not implemented by design example; behavior is unpredictable.

I/O Space BAR (any)

Not implemented by design example; behavior is unpredictable.