5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
The Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI Express with an Avalon-MM interface to the Application Layer includes an Avalon-MM bridge. This bridge translates PCI Express TLPs to standard Avalon-MM read and write commands, and vice versa. Consequently, you do not need a detailed understanding of the PCI Express TLPs to use this Avalon-MM variant.
The Avalon® -MM Intel® Arria® 10 Hard IP for PCI Express* communicates with the Application Layer in the FPGA core fabric via the following interfaces:
- RX Master (RXM): This is a bursting RX Avalon® -MM master interface that translates Memory Read and Write TLPs from the PCIe* domain to Avalon® -MM reads and writes and sends them to the slave in the Avalon® -MM memory space.
- TX Slave (TXS): This is a bursting TX Avalon® -MM slave interface that translates memory-mapped reads and writes from the Avalon® -MM domain to PCIe* Memory Read and Write TLPs and sends them to the PCIe* memory space.
- Control Register Access (CRA): This optional Avalon® -MM slave interface allows the Application Layer logic to access the internal control and status registers of the IP core.
- Hard IP Reconfiguration: This optional interface allows the Application Layer logic to dynamically modify the contents of the IP core's configuration registers that are read-only at run time.
- Hard IP Status: This optional interface contains status signals for the Hard IP to facilitate the debugging process.
- MSI/MSI-X: These interfaces provide the necessary information for the Application Layer logic to construct and send Message Signaled Interrupts to the host.
Variations using the Avalon-MM interface implement the Avalon-MM protocol described in the Avalon Interface Specifications. Refer to this specification for information about the Avalon-MM protocol, including timing diagrams.
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