Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents

5.2. Bursting and Non-Bursting Avalon® -MM Module Signals

The Avalon® -MM Master module translates read and write TLPs received from the PCIe* link to Avalon® -MM transactions for connected slaves. You can enable up to six Avalon® -MM Master interfaces. One of the six Base Address Registers (BARs) define the base address for each master interface. This module allows other PCIe* components, including host software, to access the Avalon® -MM slaves connected in the Platform Designer.
Table 26.  Avalon-MM RX Master Interface Signals <n> = the BAR number, and can be 0, 1, 2, 3, 4, or 5.

Signal Name

Direction

Description

rxm_bar<n>_write_o

Output

Asserted by the core to request a write to an Avalon-MM slave.

rxm_bar<n>_address_o[<W>-1:0]

Output

The address of the Avalon-MM slave being accessed.

rxm_bar<n>_writedata_o[<w>-1:0]

Output

RX data being written to slave. <w> = 64 or 128 for the full-featured IP core. <w> = 32 for the completer-only IP core.

rxm_bar<n>_byteenable_o[<w>-1:0]

Output

Dword enables for write data.

rxm_bar<n>_burstcount_o[6 or 5:0]

(available in burst mode only)

Output

>The burst count, measured in qwords, of the RX write or read request. The width indicates the maximum data that can be requested. The maximum data in a burst is 512 bytes. This optional signal is available for BAR2 only when you turn on Enable burst capabilities for RXM BAR2 ports.

rxm_bar<n>_waitrequest_i

Input

Asserted by the external Avalon-MM slave to hold data transfer.

rxm_bar<n>_read_o

Output

Asserted by the core to request a read.

rxm_bar<n>_readdata_i[<w>-1:0]

Input

Read data returned from Avalon-MM slave in response to a read request. This data is sent to the IP core through the TX interface. <w> = 64 or 128 for the full-featured IP core. <w> = 32 for the completer-only IP core.

rxm_bar<n>_readdatavalid_i

Input

Asserted by the system interconnect fabric to indicate that the read data is valid.

rxm_irq_i[<m>:0], <m> < 16

Input

Connect interrupts to the Avalon® -MM interface. These signals are only available for the Avalon® -MM when the CRA port is enabled. A rising edge triggers an MSI interrupt. The hard IP core converts this event to an MSI interrupt and sends it to the Root Port. The host reads the Interrupt Status register to retrieve the interrupt vector. Host software services the interrupt and notifies the target upon completion.

As many as 16 individual interrupt signals (<m>≤15) are available. If rxm_irq_<n>[<m>:0] is asserted on consecutive cycles without the deassertion of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received.
Note: These signals are not available when the IP core is operating in DMA mode (i.e. when the Enable Avalon-MM DMA option in the Avalon-MM Settings tab of the GUI is set to On).

The following timing diagram illustrates the RX master port propagating requests to the Application Layer and also shows simultaneous read and write activities.

Figure 30. Simultaneous RXM Read and RXM Write