Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.6. FPGA System Design

To integrate all components, close timing, and deliver a post-fit netlist that functions in the hardware, you must first address several additional FPGA design complexities. These design complexities include a robust reset sequence, establishment of a design floorplan, global routing management, pipelining, and IP encryption. Optimizations of these design complexities occur in tandem with one another in order to meet timing and board hardware optimization requirements.