Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.1.3. Version ID

The Stratix® V Network Reference Platform instantiates a version_id component that connects to the PCIe® Avalon® master.

Before communicating with any part of the FPGA system, the PCIe first reads from this version_id register to confirm the following:

  • The PCIe can access the FPGA fabric successfully.
  • The address map matches the map in the MMD software.

Update the VERSION_ID parameter in the version_id component to a new value with every slave addition or removal from the PCIe BAR 0 bus, or whenever the address map changes.