Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide
ID
683645
Date
11/06/2017
Public
2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
3.6.4. Global Routing
FPGAs have dedicated clock trees that distribute high fan-out signals to various sections of the devices.
In the FPGA system that the Stratix® V Network Reference Platform targets, global routing can distribute high fan-out signals in the following manners:
- Regional—Across any quadrant of the device
- Dual-regional—Across any half of the device
- Global—Across the entire device
Because there is no restriction on the placement location of the OpenCL™ kernel on the device, the kernel clocks and kernel reset must perform global distribution.
The DDR3 clock clocks all DMA logic and carries data into the QDR region at the top of the device. As a result, this clock and the reset synchronized to this clock domain also perform global distribution.