Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.6.4. Global Routing

FPGAs have dedicated clock trees that distribute high fan-out signals to various sections of the devices.

In the FPGA system that the Stratix® V Network Reference Platform targets, global routing can distribute high fan-out signals in the following manners:

  1. Regional—Across any quadrant of the device
  2. Dual-regional—Across any half of the device
  3. Global—Across the entire device

Because there is no restriction on the placement location of the OpenCL™ kernel on the device, the kernel clocks and kernel reset must perform global distribution.

The DDR3 clock clocks all DMA logic and carries data into the QDR region at the top of the device. As a result, this clock and the reset synchronized to this clock domain also perform global distribution.