2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
1.1. Stratix V Network Reference Platform: Prerequisites
The Stratix V Network Reference Platform Porting Guide assumes that you are an experienced FPGA designer who is familiar with Intel® 's FPGA design tools and concepts.
These design tools and concepts include:
- FPGA architecture, including clocking, global routing and I/Os
- High-speed design
- Timing analysis
- Intel® Quartus® Prime software
- Platform Designer (Standard) design and Avalon® interfaces
- Tcl scripting
- Designing with Logic Lock regions
- PCI Express* ( PCIe* )
- DDR3 external memory
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