Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.2.3. DDR3 Connection to OpenCL Kernel

The OpenCL™ kernel needs to connect directly to the memory controller via a FIFO-based clock crosser.

A clock crosser is necessary because the kernel interface for the compiler must be clocked in the kernel clock domain. In addition, the width, address width, and burst size characteristics of the kernel interface must match those specified in the bank divider connecting to the host. Appropriate pipelining also exists between the clock crosser and the memory controller.