Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.6.5. Pipelining

To implement pipelining in Platform Designer (Standard), refer to the Platform Designer (Standard) Interconnect chapter of the Intel® Quartus® Prime Standard Edition Handbook for more information.

Below are some specific examples of pipelining:

  • Signals that traverse long distances because of the floorplan require additional pipelining.

    The DMA at the bottom of the FPGA must connect to the QDR memory at the top of the FPGA. QDR provides a 64-bit-wide interface at 275 MHz. The DMA is 512 bits in width at 200 MHz. This latter connection is converted to a 128-bit-wide 200 MHz interface in the pipe_stage_qdr_host_0 module, which is pipelined in both command and response. This narrower bus enables crossing from the bottom region to the QDR region at the top, where it goes directly into pipe_stage_qdr_host_1. The configuration of the pipe_stage_qdr_host_1 module is similar to pipe_stage_qdr_host_0 to ensure no logic insertion between the two regions. This setup effectively implements pipelined routing in the 200 MHz clock domain, which the clock crosses into the 275 MHz domain. Finally, the width of the clock domain is adapted to ensure that this entire connection can still fully saturate the QDR bandwidth.

  • The OpenCL™ kernel might need to connect the DDR interfaces at the bottom of the device and the QDR kernel interfaces at the top of the device.

    The kernel interfaces for QDR memory are located in the top region of the FPGA. However, the host and DDR connections originate from the bottom region of the FPGA. This distribution can force the kernel to stretch across the vertical span of the device, resulting in a slower Fmax. To minimize the decrease in Fmax, enable additional pipelining in the kernel when connecting to QDR memory. Add an addpipe attribute to each of the QDR interface element in board spec.xml, and assign it a value of 1.