Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.1. Host-FPGA Communication over PCIe

To set up the PCIe® hard IP that enables communication between the host and the FPGA board, you must configure the IP settings, and set various IDs, constants and parameters.

Did you find the information on this page useful?

Characters remaining:

Feedback Message