Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.8. Addition of Timing Constraints

A Custom Platform must apply the correct timing constraints to the Intel® Quartus® Prime project. In the Stratix® V Network Reference Platform, the top.sdc file contains all timing constraints applicable before IP instantiation in Platform Designer (Standard). The top_post.sdc file contains timing constraints applicable after Platform Designer (Standard). The order of the application is based on the order of appearance of the top.sdc and top_post.sdc in the top.qsf file.

One noteworthy constraint in s5_net is the multicycle constraint for the kernel reset in the top_post.sdc file. Using global routing saves routing resources and provides more balanced skew. However, the delay across the global route might cause recovery timing issues that limit kernel clock speed. Although Intel® requires all logic to exit reset mode in the same clock cycle, it is not necessary for the exit to happen in the same clock cycle as reset deassertion. Therefore, Intel® adds a multicycle setup constraint of 2 and multicycle hold of 1 to the kernel reset. Without these additions, even with reset drivers located directly adjacent to global clock buffers, the highest kernel Fmax that Intel® achieves is around 320 MHz.