Visible to Intel only — GUID: ewa1405011168963
Ixiasoft
Visible to Intel only — GUID: ewa1405011168963
Ixiasoft
3.5.1. QuickUDP IP Instantiation
The two 10 Gigabit Media Independent Interface (XGMII) interfaces from these cores connect to a single 10GBASE-R PHY with two channels. The Verilog instantiation of the PHY IP core is in the <path_to_s5_net>/hardware/s5_net/ip/quickudp/quickudp_wrapper.v file. This file contains parameters such as the multitenant unit (MTU) and the number of sessions supported. Most parameters are accessible via QuickUDP's Avalon® Memory-Mapped (Avalon-MM) slave interface.
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