Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.5.1. QuickUDP IP Instantiation

The Stratix® V Network Reference Platform targets a computing card that has two 10 GbE channels. To access these channels, s5_net instantiates two PLDA QuickUDP IP cores.

The two 10 Gigabit Media Independent Interface (XGMII) interfaces from these cores connect to a single 10GBASE-R PHY with two channels. The Verilog instantiation of the PHY IP core is in the <path_to_s5_net>/hardware/s5_net/ip/quickudp/quickudp_wrapper.v file. This file contains parameters such as the multitenant unit (MTU) and the number of sessions supported. Most parameters are accessible via QuickUDP's Avalon® Memory-Mapped (Avalon-MM) slave interface.