Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™

After you modify your Intel® Quartus® Prime design files, integrate your Custom Platform with the Intel® FPGA SDK for OpenCL™ .
  1. Update the <your_custom_platform_name>/hardware/<board_name>/board_spec.xml file by removing the QDR and Ethernet channels from it. Ensure that there is at least one global memory interface, and all the global memory interfaces correspond to the exported interfaces from the board.qsys Platform Designer (Standard) system file.
    QDR section of the Stratix® V Network Reference Platform's board_spec.xml file:
    <!-- QDRII -->
    <global_mem name="QDR" max_bandwidth="17600" interleaved_bytes="8"
        <interface name="board" type="slave" width="64" maxburst="1"
    	 address="0x200000000" size="0x1000000" latency="150" addpipe="1">
            <port name="kernel_qdr0_r" direction="r"/>
            <port name="kernel_qdr0_w" direction="w"/>
        <interface name="board" type="slave" width="64" maxburst="1"
    	 address="0x201000000" size="0x1000000" latency="150" addpipe="1">
            <port name="kernel_qdr1_r" direction="r"/>
            <port name="kernel_qdr1_w" direction="w"/>
        <interface name="board" type="slave" width="64" maxburst="1"
    	 address="0x202000000" size="0x1000000" latency="150" addpipe="1">
            <port name="kernel_qdr2_r" direction="r"/>
            <port name="kernel_qdr2_w" direction="w"/>
        <interface name="board" type="slave" width="64" maxburst="1"
    	 address="0x203000000" size="0x1000000" latency="150" addpipe="1">
            <port name="kernel_qdr3_r" direction="r"/>
            <port name="kernel_qdr3_w" direction="w"/>

    Ethernet channels section of the s5_net board_spec.xml file:
        <interface name="udp_0" port="udp0_out"  type="streamsource" width="256"
        <interface name="udp_0" port="udp0_in"  type="streamsink" width="256"
        <interface name="udp_0" port="udp1_out"  type="streamsource" width="256"
        <interface name="udp_0" port="udp1_in"  type="streamsink" width="256"

  2. In the <your_custom_platform_name>/hardware/<board_name>/scripts directory, modify the post_flow.tcl file to not call the create_fpga_bin.tcl file. You can do so by commenting out the line of code containing the command call_script_as_function scripts/create_fpga_bin.tcl.
    # Generate fpga.bin used for reprogramming
    post_message "Generating fpga.bin"
    if {[catch { call_script_as_function scripts/create_fpga_bin.tcl $revision_name.sof
         $revision_name.core.rbf $revision_name.periph_hash $revision_name } res]}
        post_message -type error "Error in create_fpga_bin.tcl! $res"
        exit 2
  3. Set the environment variable ACL_QSH_COMPILE_CMD to quartus_sh --flow compile top -c base.
    Setting this environment variable instructs the SDK to compile the base revision corresponding to the base.qsf file in the <your_custom_platform_name>/hardware/<board_name> directory of your Custom Platform.
  4. Perform the steps outlined in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/README.txt file to compile the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/ OpenCL kernel source file.
    The environment variable INTELFPGAOCLSDKROOT points to the location of the SDK installation.
    The hardware compilation stage will fail because of the absence of the fpga.bin file. However, the Intel® Quartus® Prime compilation should complete successfully and produce a boardtest.aoco Intel® FPGA SDK for OpenCL™ Offline Compiler object file.
  5. If compilation fails because of timing failures, fix the errors, or compile INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/ with different seeds by including the -seed=<N> option in the aoc command (for example, aoc -seed=2