Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.7.3. Provide a Timing-Closed Post-Fit Netlist

Provide a timing-closed post-fit netlist that imports placement and routing information for all nodes clocked by nonkernel clocks.
Intel® provides several mechanisms for preserving the placement and routing of some previously-compiled logic and for importing it into a new compilation. For the Stratix® V Network Reference Platform, the following features are desirable from such a flow:
  1. Timing preservation
  2. Version compatibility to allow the import of the netlist into a newer Intel® Quartus® Prime software version
  3. Strict preservation of the FPGA periphery to guarantee successful CvP programming

The Intel® FPGA CvP compilation flow for the Stratix V device provides all of these features through an exported .personax file for the top-level partition. This means s5_net is configured with the project revisions and partitions necessary for implementing this flow. By default, the Intel® FPGA SDK for OpenCL™ invokes the Intel® Quartus® Prime software on revision top. This revision is configured to import the persona/base.root_partition.personax file, which has been precompiled and exported from a base revision compilation.

For more information, refer to the CvP section.