Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents Specifying Configuration via PCI Express Options

To enable Configuration via Protocol programming of the FPGA core logic, specify the configuration via PCIe™ options in the Intel® Quartus® Prime software.
  1. In the Stratix V HIP for PCI Express parameter editor GUI, under System Settings, select Enable configuration via the PCIe link to enable CvP on the PCIe IP.
  2. Include the following INI settings in the quartus.ini file:
    skip_hssi_gen3_pcie_hip_cvp_enable_rule = on
    skip_hssi_gen3_pcie_hip_hip_hard_reset_rule = on
    skip_hssi_gen3_pcie_hip_hrdrstctrl_en_rule = on
  3. In the Intel® Quartus® Prime software, click Assignments > Device > Device and Pin Options to open the Device and Pin Options dialog box.
  4. Under General, select Enable autonomous PCIe HIP mode.
  5. Under CvP Settings, perform the following tasks:
    1. Set Configuration via Protocol to Core update.
    2. Select Enable CvP_CONFDONE pin.
    3. Select Enable open drain on CvP_CONFDONE pin.

The PCIe core must have the force_hrc parameter set to a value of 1 in the board.qsys file. Because you cannot set this parameter using the Platform Designer (Standard) GUI, you must save and exit Platform Designer (Standard), and then edit the setting in the board.qsys file.


Depending on whether the PCIe core is used in the base or CvP revision, additional modifications to the PCIe controller behavior might be necessary. An additional multpersona partition named cvp_update_reset_partition is implemented to work in conjunction with the following file edits:

  • Replacement of altpcie_sv_hip_ast_hwtcl.v and altpcie_hip_256_pipen1b.v in the <path_to_OpenCL_kernel_filename_directory>/system/synthesis/submodules directory.
  • Addition of cvp_update_reset.v (for base revision) and cvp_update_reset_zero.v (for CvP update revision) in the <path_to_OpenCL_kernel_filename_directory>/system/synthesis/submodules directory.

After Platform Designer (Standard) Verilog generation and before launching the Intel® Quartus® Prime compilation, the <path_to_s5_net>/hardware/s5_net/scripts/pre_flow.tcl Tcl script performs these file edits automatically. The following Verilog source files reside in the INTELFPGAOCLSDKROOT/ip/board/migrate/cvpupdatefix directory, where INTELFPGAOCLSDKROOT points to the Intel® FPGA SDK for OpenCL™ installation directory:

  • altpcie_sv_hip_ast_hwtcl.v
  • altpcie_hip_256_pipen1b.v
  • cvp_update_reset.v
  • cvp_update_reset_zero.v