2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.5.2. QuickUDP Configuration via PCIe-Based Host
The Stratix® V Network Reference Platform provides access to the PLDA QuickUDP IP configuration space to the host over PCIe® by connecting pipe_stage_host_ctrl to the config_udp0 and config_udp1 interfaces of the s5_net udp.qsys subsystem.
Intel® FPGA SDK for OpenCL™ users need to set their own parameters such as media access control (MAC), IP address, ports, and destinations. With the host access to QuickUDP via PCIe, the SDK users can configure the QuickUDP settings in their host software using the API in the <path_to_s5_net>/include/aocl_net.h header file.
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