Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.5.2. QuickUDP Configuration via PCIe-Based Host

The Stratix® V Network Reference Platform provides access to the PLDA QuickUDP IP configuration space to the host over PCIe® by connecting pipe_stage_host_ctrl to the config_udp0 and config_udp1 interfaces of the s5_net udp.qsys subsystem.

Intel® FPGA SDK for OpenCL™ users need to set their own parameters such as media access control (MAC), IP address, ports, and destinations. With the host access to QuickUDP via PCIe, the SDK users can configure the QuickUDP settings in their host software using the API in the <path_to_s5_net>/include/aocl_net.h header file.