2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
|Intel® Quartus® Prime Design Suite 17.1|
The Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide describes the procedures and design considerations you can implement to modify the Stratix® V Network Reference Platform (s5_net) into your own Custom Platform for use with the Intel® FPGA Software Development Kit (SDK) for OpenCL™ 1 2. This document also contains reference information on the design decisions for s5_net, which makes use of features such as heterogeneous memory buffers and I/O channels to maximize hardware usage on a computing card designed for networking.
Stratix V Network Reference Platform: Prerequisites
Features of the Stratix V Network Reference Platform
Contents of the Stratix V Network Reference Platform
1 OpenCL™ and the OpenCL logo are trademarks of Apple Inc. used by permission of the Khronos Group™.
2 The Intel® FPGA SDK for OpenCL™ is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
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