Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

A. Document Revision History

Table 10.  Document Revision History of the Stratix V Network Reference Platform Porting Guide
Date Version Changes
November 2017 2017.11.03
  • Rebranded the following:
    • Environment variable ALTERAOCLSDKROOT to INTELFPGAOCLSDKROOT.
    • Environment variable CL_CONTEXT_COMPILER_MODE_ALTERA to CL_CONTEXT_COMPILER_MODE_INTELFPGA
    • USB Blaster Cable to Intel FPGA Download Cable.
    • SignalTap II Logic Analyzer to Signal Tap logic analyzer.
    • Quartus Prime to Intel® Quartus® Prime
    • LogicLock to Logic Lock
    • Qsys to Platform Designer (Standard)
  • Implemented single dash and -option=<value> conventions in the following topics:
  • Added a new topic aocl list-devices.
  • Updated the topic aocl diagnose to include support for diagnosing multiple devices and all devices.
  • Updated the topics aocl install and aocl uninstall to include the path to custom platform during installation and uninstallation.
  • In Establishing Host Communication, removed reference to the environment variable AOCL_BOARD_PACKAGE_ROOT since it is deprecated and updated instances of aocl install updated as aocl install <path_to_customplatform>.
May 2017 2017.05.08
  • Maintenance release.
October 2016 2016.10.31
  • Rebranded Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
  • Rebranded Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
  • In Building the Software in Your Custom Platform, updated the code snippet in Step 4 from #define ACL_VENDOR_NAME "Altera Corporation" to #define ACL_VENDOR_NAME "Intel(R) Corporation".
May 2016 2016.05.02 Maintenance release.
November 2015 2015.11.02 Maintenance release, and made the following updates:
  • Changed instances of Quartus® II to Quartus® Prime.
  • Changed instances of Altera® Complete Design Suite to Intel® Quartus® Prime Design Suite .
May 2015 15.0.0 Maintenance release.
December 2014 14.1.0
  • Renamed the document as Altera Stratix V Network Reference Platform Porting Guide.
  • Updated the Legacy Board Support section. Added reference to the Custom Platform Automigration for Forward Compatibility section in the Altera SDK for OpenCL Custom Platform Toolkit User Guide for automigration information and instructions.
  • In the Implementation of UDP Cores as OpenCL Channels section, added notes indicating the following:
    1. The QuickUDP IP requires a license from PLDA.
    2. Improper installation of the PLDA QuickUDP license causes the Altera® Software Development Kit (SDK) for OpenCL™ (AOCL) users to encounter a compilation error.
  • In the Describe the s5_net Hardware to the AOCL section:
    1. Elaborated on the calculation of the value for used_resources based on the values reported in the Fitter report.
    2. Added information on the compile and board board_spec.xml XML elements.
  • Added an aocl uninstall subsection under OpenCL Utilities Implementation to document the locations of the uninstall script for Windows and Linux systems.
July 2014 14.0.0 Initial Release.
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