Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.6.3. Floorplan

The Intel® FPGA SDK for OpenCL™ requires all board logic to be constrained along the edges of the FPGA device. This constraint provides a large contiguous space for OpenCL kernel implementation, which generally leads to better circuit performance (that is, Fmax).

The Stratix® V Network Reference Platform floorplan below shows that all board interface logic are along the edges of the device. The logic in the center is the OpenCL kernel. At the bottom of the device are the PCIe® and the two DDR3 cores. The QDR controllers are along the top of the device, and the two UDP stacks are on the right. The Stratix V global clock buffers are all around the middle of the device. This floorplan accommodates access to the global clock buffers by extending the bottom region edges up the left and right sides. This extension allows the placement of reset and other global routing drivers in the bottom region to be near the global clock buffer.

Figure 2. S5_net Floorplan

You can derive a floorplan for any board by following these steps:

  1. Compile the design without any region constraints.
  2. Examine the placement location of each of the IP cores in the Chip Planner.
  3. Apply Logic Lock regions to push the IP cores to the edges of the device.