Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

2.10. Guaranteeing Timing Closure

When you modify the Stratix® V Network Reference Platform into your own Custom Platform, ensure that guaranteed timing closure holds true for your Custom Platform.
  1. Establish the floorplan of your design.
    Important: Consider all design criteria outlined in FPGA System Design and the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
  2. Compile several seeds of until you generate a compiled design that achieves timing closure cleanly. Include the -seed=<N> option in your aoc command to specify the seed number.
  3. Copy the <path_to_s5_net>/hardware/s5_net/persona/base.root_partition.personax file into your Custom Platform.
  4. Copy the boardtest.aocx file from the timing-closed compilation in Step 2 into your Custom Platform. Rename the file base.aocx.
  5. Derive the top revision top.qsf file from your base.qsf file by including the changes described in the CvP section.
  6. Remove the ACL_QSH_COMPILE_CMD environment variable.
  7. Recompile In the Fitter Preservation section of the report, confirm that the Top partition is imported.
    The Incremental Compilation Placement Preservation section should show 100% placement for Top. Similarly, the Incremental Compilation Routing Preservation section should show 100% routing for Top.
  8. Confirm that you can use the .aocx file to reprogram over CvP by invoking the aocl program acl0 boardtest.aocx command.
  9. Ensure that the environment variable CL_CONTEXT_COMPILER_MODE_INTELFPGA is not set. Run the boardtest_host executable.