Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

2.2. Removing Unused Hardware

After you store the Stratix™ V Network Reference Platform to your own directory and perform some preliminary modifications, modify the Intel® Quartus® Prime design files.
  1. Instantiate your PCIe® controller.
    For detailed instructions on instantiating your PCIe controller, refer to the Getting Started with the Avalon-MM Stratix V Hard IP for PCI Express section of the Stratix V Avalon-MM Interface for PCIe Solutions User Guide.

    For information on the design parameters for instantiating the PCIe controller in s5_net, refer to Host-FPGA Communication over PCIe, and the Parameter Settings section of the Stratix V Avalon-MM Interface for PCIe Solutions User Guide.

  2. In Platform Designer (Standard), open the <your_custom_platform_name>/hardware/<board_name>/board.qsys Platform Designer (Standard) system file. Remove the following components by selecting their names and then clicking Remove from the right-click menu:
    1. cpld_bridge_0
    2. qdr_0
    3. DDR3 memory controllers
      Because several components use the clock that ddr3a generates, it might be easier to remove only the second DDR3 controller (ddr3b) and reparameterize ddr3a to match your memory.
  3. Remove the cpld.sdc file from the <your_custom_platform_name>/hardware/<board_name> directory.
  4. In Platform Designer (Standard), open the <your_custom_platform_name>/hardware/<board_name>/system.qsys file. Remove the udp_0 component.
  5. In the Platform Designer (Standard) System menu, click Remove Dangling Connections to remove invalid connection points between system.qsys and board.qys.
  6. Modify both Intel® Quartus® Prime settings files (.qsf) to use only the pin-outs and settings for your system. Ensure that the only differences between the base.qsf and top.qsf files are in the settings in the Revision Specific Settings section of the files.