Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents Replacing FPGA Core Logic via CvP Programming

To successfully program the FPGA core logic, the Fitter must ensure that all FPGA periphery programming bits remain unchanged. The CvP revision flow expresses this hard constraint to the Fitter. Use the Stratix® V Network Reference Platform CvP revision flow to achieve reliable CvP programming of the core logic.
  1. Create a base revision. In the Stratix V Network Reference Platform, the base revision is the <path_to_s5_net>/hardware/s5_net/base.qsf file.
  2. Create a CvP update revision.
    This update version is derived from the base revision and includes an imported .personax file. The .personax file is created during a base revision compilation. It includes the root partition imported from the base revision compilation. In s5_net, this CvP update revision is the top.qsf file, which becomes the project revision that the Intel® FPGA SDK for OpenCL™ Offline Compiler compiles by default.

  3. Create a kernel partition in both base and update revisions (marked as having multiple personas).
  4. Store the base revision compilation programming file output in the Flash memory as the power-up configuration.
  5. Use the CvP update revision compilation programming file output for all subsequent FPGA configurations.

Did you find the information on this page useful?

Characters remaining:

Feedback Message