Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.3. QDRII as Heterogeneous Memory for OpenCL Applications

The OpenCL™ heterogeneous memory feature allows Intel® FPGA SDK for OpenCL™ users to take advantage of the nonuniform memory architecture in a Custom Platform.

An SDK Custom Platform groups memories with similar characteristics into a single global memory system. Each Custom Platform has a designated default global memory system. In the case of the Stratix® V Network Reference Platform, the default global memory system consists of the two DDR3 memory banks. The default global memory system must start at base address 0 from the host's perspective. Both the hardware design and the board_spec.xml file in the Custom Platform reflect this address assignment. In s5_net, the DDR global memory system is named DDR.

In addition to the DDR global memory system, the computing card that s5_net targets includes four banks of QDR memory. These four banks belong to a global memory system named QDR. SDK users can only allocate memory in the QDR global memory system using an attribute on their global memory buffers. All addressable global memory must be contiguous from the host's perspective; therefore, the QDR memory base address must start where the DDR memory ends.

For more information on the QDR UniPHY IP, refer to the QDR II and QDR IV SRAM Board Design Guidelines in Volume 2 of the External Memory Interface Handbook.

The procedure for implementing the QDR subsystem is similar to the one outlined in the Developing Your Custom Platform section. Below is a list of high-level tasks:

  1. Instantiate and parameterize the UniPHY memory controllers.
  2. Connect the UniPHY memory controllers to the host via a new OpenCL Memory Bank Divider instance.
  3. Connect the UniPHY memory controller to the UniPHY Status to AVS component.
  4. Export the UniPHY memory controller to the OpenCL kernel via clock-crossing bridges.

Below are special QDR subsystem design considerations for s5_net:

  • QDR provides separate read and write ports.

    By default, the OpenCL Memory Bank Divider produces a single bidirectional master for each memory controller. In Platform Designer (Standard), select the Separate read/write ports option to support separate read and write masters. With respect to the kernel, instantiate clock crosses and separate read and write interfaces.

  • The 275 MHz QDR afi clock and 4-to-1 multiplexing in the bank divider make it difficult to meet timing.

    To achieve timing closure robustly, open the qdr.qsys file in Platform Designer (Standard), and select the option to pipeline the outputs in the OpenCL Memory Bank Divider memory_bank_divider_1. Doing so adds a pipeline stage for each master that the bank divider creates.