Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

1.2. Features of the Stratix V Network Reference Platform

Prior to designing an Intel® FPGA SDK for OpenCL™ Custom Platform, decide on design considerations that allow you to fully utilize the available hardware on your computing card.
Figure 1. Hardware Features on a Hypothetical Stratix V Network Reference Platform Computing Card

Features of s5_net:

  1. OpenCL Host

    A PCIe®-based host that connects to the Stratix V PCIe Gen2 x8 hard intellectual property (IP) core.

  2. OpenCL Global Memory

    The hardware provides two separate 4-gigabyte (GB) DDR3 memory buffers. S5_net uses both banks together to create 8 GB of global memory.

  3. Heterogeneous Memory

    S5_net uses the four on-board quad data rate II (QDRII) memory interfaces to implement a total of 64 megabytes (MB) of heterogeneous memory for the Intel® FPGA SDK for OpenCL™ Offline Compiler. By default, the host application allocates memory into the OpenCL global memory (that is, DDR3) when an OpenCL kernel program loads into the OpenCL runtime. However, based on the kernel arguments, the host might relocate memory to other buffers available on the computing card (that is, QDRII). Accesses to heterogeneous memory buffers are advantageous for network applications because they require the fast random access bandwidth that QDR provides.

  4. OpenCL I/O Channels

    The two 10 Gbps Ethernet (10 GbE) I/Os connect to a full user datagram protocol (UDP) stack that provides an Avalon® Streaming (Avalon-ST) interface for direct connection to OpenCL kernels.

  5. FPGA Programming

    The computing card uses the Configuration via Protocol (CvP)-capable PCIe hard IP. S5_net uses Intel® FPGA CvP feature for implementing fast reprogramming over PCIe.

  6. Guaranteed Timing

    Guaranteed timing closure is achievable via the Intel® Quartus® Prime compilation flow for CvP. S5_net delivers a precompiled netlist in a .personax file that the offline compiler imports into each kernel compilation.