1.2. Features of the Stratix V Network Reference Platform
Features of s5_net:
- OpenCL Host
A PCIe®-based host that connects to the Stratix V PCIe Gen2 x8 hard intellectual property (IP) core.
- OpenCL Global Memory
The hardware provides two separate 4-gigabyte (GB) DDR3 memory buffers. S5_net uses both banks together to create 8 GB of global memory.
- Heterogeneous Memory
S5_net uses the four on-board quad data rate II (QDRII) memory interfaces to implement a total of 64 megabytes (MB) of heterogeneous memory for the Intel® FPGA SDK for OpenCL™ Offline Compiler. By default, the host application allocates memory into the OpenCL global memory (that is, DDR3) when an OpenCL kernel program loads into the OpenCL runtime. However, based on the kernel arguments, the host might relocate memory to other buffers available on the computing card (that is, QDRII). Accesses to heterogeneous memory buffers are advantageous for network applications because they require the fast random access bandwidth that QDR provides.
- OpenCL I/O Channels
The two 10 Gbps Ethernet (10 GbE) I/Os connect to a full user datagram protocol (UDP) stack that provides an Avalon® Streaming (Avalon-ST) interface for direct connection to OpenCL kernels.
- FPGA Programming
The computing card uses the Configuration via Protocol (CvP)-capable PCIe hard IP. S5_net uses Intel® FPGA CvP feature for implementing fast reprogramming over PCIe.
- Guaranteed Timing
Guaranteed timing closure is achievable via the Intel® Quartus® Prime compilation flow for CvP. S5_net delivers a precompiled netlist in a .personax file that the offline compiler imports into each kernel compilation.
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