Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide
ID
683645
Date
11/06/2017
Public
2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
3.5. Implementation of UDP Cores as OpenCL Channels
OpenCL™ kernels can communicate directly with I/O using the Intel® FPGA SDK for OpenCL™ channels extension.
For the Stratix® V Network Reference Platform, Intel® uses the PLDA QuickUDP IP to implement a full UDP stack on top of the available 10 GbE channels on the card. QuickUDP provides an Avalon®-ST interface that can connect directly to the OpenCL kernel, allowing it to send and receive UDP network traffic without concern for UDP or lower-level protocols.
Attention: The UDP Hardware Stack QuickUDP IP is a licensed IP from PLDA. Refer to the PLDA website for information on acquiring and installing the appropriate license.
CAUTION:
Improper installation of the QuickUDP IP license causes the SDK users to encounter the following error message when they compile with a Custom Platform that contains the QuickUDP IP:
Error (292014): Can't find valid feature line for core PLDA QUICKTCP (73E1_AE12) in current license.
The error has no actual dependency on the PLDA QuickTCP IP.
Section Content
QuickUDP IP Instantiation
QuickUDP Configuration via PCIe-Based Host
QuickUDP Connection to OpenCL Kernel
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