Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.6.6. Encrypted IPs

The Stratix® V Network Reference Platform incorporates two encrypted IP cores. They are the PLDA QuickUDP IP and the CPLD_bridge IP. The CPLD_bridge IP enables communication between the FPGA and external CPLD.

Incorporation of these IP cores in s5_net demonstrates that it is feasible to use the Intel® FPGA encryption infrastructure to encrypt IPs within a Custom Platform.

Contact your field application engineer for more information on how to encrypt IP for use with the Intel® Quartus® Prime software.