Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.5.3. QuickUDP Connection to OpenCL Kernel

Each PLDA QuickUDP IP core produces a read stream and a write stream, for a total of four Intel® FPGA SDK for OpenCL™ channels available to the kernel. These streams cross into the kernel clk domain and are listed in the board spec.xml file.
Attention: The SDK supports only basic Avalon®-ST with no packet support.

QuickUDP provides an Avalon-ST interface with full packet support along with additional metadata about the payload. Because OpenCL does not support the packet extensions, the packetization signals are converted to data, and the OpenCL application must handle all packetization.

QuickUDP also provides additional metadata that the application can use. For a full explanation of these signals, refer to the QuickUDP documentation on the PLDA website. In the Stratix® V Network Reference Platform, the payload, packetization signals, and metadata are concatenated into a single 256-bit-wide vector exported as an Intel® FPGA SDK for OpenCL™ channel.

Use the information in the following table to access the desired components of the channel's data:

Table 8.  Bit Mapping for the 256-Bit Intel® FPGA SDK for OpenCL™ Channel to QuickUDP
Bit Range Name Description
[0:127] payload Packet payload
[128] sop Start of packet signal
[129] eop End of packet (EOP) signal
[130:133] empty On EOP, this field indicates how many bytes are unused
[134:149] payload_size Size of the packet

Set to 0 for outbound packets

[150:181] rem_ip Indicates the remote IP for incoming packets
[182:197] rem_port Indicates the remote port for incoming packets
[198:205] channel Avalon channel
[206] error Avalon error signal