Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.6.1. Clocks

The following clock domains affect the Platform Designer (Standard) hardware system:

  • 250 MHz PCIe® clock
  • 200 MHz DDR3 clock
  • 275 MHz QDR clock
  • 156.25 MHz Ethernet clock
  • 100 MHz general clock (config_clk)
  • Kernel clock that can take on any clock frequency

With the exception of the kernel clock, the Stratix® V Network Reference Platform is responsible for closing timing of these clocks. However, because the board design must clock cross all interfaces in the kernel clock domain, the board design also has logic in this clock domain. It is crucial that this logic is minimal and achieves an Fmax higher than typical kernel performance.