Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.10.1. CvP

The CvP feature enables core logic update over the PCIe® hard IP for Stratix® V and Arria® V GZ devices. Refer to the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide for more information.