Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

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ID 683645
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide 2. Developing Your Custom Platform 3. Stratix V Network Reference Platform Design Architecture A. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide x
1.1. Stratix V Network Reference Platform: Prerequisites 1.2. Features of the Stratix V Network Reference Platform 1.3. Contents of the Stratix V Network Reference Platform
1.1. Stratix V Network Reference Platform: Prerequisites x
1.1.1. Legacy Board Support
2. Developing Your Custom Platform x
2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
2.4. Setting up the Software Development Environment x
2.4.1. Setting Up Software Development Environment for Windows 2.4.2. Setting Up the Software Development Environment for Linux
3. Stratix V Network Reference Platform Design Architecture x
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
3.1. Host-FPGA Communication over PCIe x
3.1.1. Parameter Settings for PCIe Instantiation 3.1.2. PCIe Device Identification Registers 3.1.3. Version ID 3.1.4. Definitions of Hardware Constants in Software Header Files 3.1.5. PCIe Kernel Driver 3.1.6. SG-DMA
3.2. DDR3 as Global Memory for OpenCL Applications x
3.2.1. DDR3 IP Instantiation 3.2.2. DDR3 Connection to PCIe Host 3.2.3. DDR3 Connection to OpenCL Kernel
3.5. Implementation of UDP Cores as OpenCL Channels x
3.5.1. QuickUDP IP Instantiation 3.5.2. QuickUDP Configuration via PCIe-Based Host 3.5.3. QuickUDP Connection to OpenCL Kernel
3.6. FPGA System Design x
3.6.1. Clocks 3.6.2. Resets 3.6.3. Floorplan 3.6.4. Global Routing 3.6.5. Pipelining 3.6.6. Encrypted IPs
3.7. Guaranteed Timing Closure x
3.7.1. Supply the Kernel Clock 3.7.2. Guarantee Kernel Clock Timing 3.7.3. Provide a Timing-Closed Post-Fit Netlist
3.9. Connection to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe s5_net to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the s5_net Hardware to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow x
3.10.1. CvP 3.10.2. Flash 3.10.3. Defining the Contents of the fpga.bin File
3.10.1. CvP x
3.10.1.1. Replacing FPGA Core Logic via CvP Programming 3.10.1.2. Specifying Configuration via PCI Express Options 3.10.1.3. Base versus CvP Update Revisions in CvP Programming
3.12. OpenCL Utilities Implementation x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
1. Intel® FPGA SDK for OpenCL™ Stratix® V Network Reference Platform Porting Guide
2. Developing Your Custom Platform
3. Stratix V Network Reference Platform Design Architecture
A. Document Revision History

3.10.1.3. Base versus CvP Update Revisions in CvP Programming

Base revision and CvP update revision have separate but almost identical Intel® Quartus® Prime Settings Files named base.qsf and top.qsf, respectively.

The base.qsf file includes the following parameter settings: 

set_global_assignment -name VERILOG_FILE system/synthesis/submodules/cvp_update_reset.v
set_global_assignment -name CVP_REVISION top
set_global_assignment -name ROUTING_BACK_ANNOTATION_FILE super_kernel_clock.rcf

The top.qsf file includes the following parameter settings: 

set_global_assignment -name VERILOG_FILE system/synthesis/submodules/cvp_update_reset_zero.v
set_global_assignment -name REVISION_ TYPE CVP
set_global_assignment -name BASE_REVISION base
set_global_assignment -name INPUT_PERSONA persona/base.root_partition.personax -section_id Top
Figure 4. Base and CvP Revisions in top.qpfWhen you open the top-level Intel® Quartus® Prime Project File <path_to_s5_net>/hardware/s5_net/top.qpf in the Intel® Quartus® Prime software, the Project Navigator displays the base revision (base) and the CvP revision (top).
Figure 5. Base Revision Design PartitionsWhen you click Assignments > Design Partitions Window, the Design Partitions window lists two defined design partitions for the base revision.
  • acl_kernel_partition contains all kernel-related logic.
  • cvp_update_reset_partition contains the fix that works in conjunction with the pre_flow.tcl script to modify the PCIe® controller behavior.

For both partitions, the Allow Multiple Personas parameter is set to On. This setting indicates that the board interface logic remains unchanged, but these partitions might change across different compilations. The acl_kernel_partition comprises of different kernel logic resulting from the compilation of the OpenCL kernel source code, as shown below:

Figure 6. CvP Revision Design PartitionsThe Top partition, which contains everything other than acl_kernel_partition and cvp_update_reset_partition, preserves placement-and-routing by importing the input persona persona/base.root_partition.personax file.

In the case of a base revision compilation, invoking the export_persona -overwrite -partition Top Tcl command exports the persona/base.root_partition.personax file from the <path_to_s5_net>/hardware/s5_net/scripts/post_flow.tcl file. This .personax file is imported into all subsequent CvP update revision compilations. It preserves the placement and routing of all non-kernel-related logic so that CvP updates only change the logic residing in the kernel partition. Within the kernel partition, the kernel_system.qsys system is automatically generated at compilation time. It is a Platform Designer (Standard) subhierarchy of system.qsys. It contains one or more kernel IPs and wrapper logic to connect the kernel partition to the OpenCL board logic in board.qsys and the UDP logic in udp.qsys.

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