Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide

ID 683645
Date 11/06/2017
Document Table of Contents

3.2.2. DDR3 Connection to PCIe Host

Connect all global memory systems to the host via the OpenCL™ Memory Bank Divider component.

The DDR3 UniPHY IP core has two banks where their width and address configurations match those of the DDR3 SDRAM. Intel® tunes the other parameters such as burst size, pending reads, and pipelining. These parameters are customizable for an end application or board design.

The Avalon® master interfaces from the bank divider connect to their respective memory controllers. The Avalon slave connects to the PCIe® and DMA cores. Implementations of appropriate clock crossing and pipelining are based on the design floorplan and clock domains specific to the computing card. The OpenCL Memory Bank Divider section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide specifies the connection details of the snoop and memorg ports.

Important: Instruct the host to check for the successful calibration of the memory controller.

The board.qsys system uses a custom IP component named UniPHY Status to AVS to aggregate different UniPHY status conduits into a single Avalon slave port named s. This slave connects to the pipe_stage_host_ctrl component so that the PCIe host can access it.