2.1. Initializing Your Custom Platform 2.2. Removing Unused Hardware 2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Software Development Environment 2.5. Building the Software in Your Custom Platform 2.6. Establishing Host Communication 2.7. Connecting the Memory 2.8. Integrating an OpenCL Kernel 2.9. Programming Your FPGA Quickly Using CvP 2.10. Guaranteeing Timing Closure 2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe 3.2. DDR3 as Global Memory for OpenCL Applications 3.3. QDRII as Heterogeneous Memory for OpenCL Applications 3.4. Host Connection to OpenCL Kernels 3.5. Implementation of UDP Cores as OpenCL Channels 3.6. FPGA System Design 3.7. Guaranteed Timing Closure 3.8. Addition of Timing Constraints 3.9. Connection to the Intel® FPGA SDK for OpenCL™ 3.10. FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. OpenCL Utilities Implementation 3.13. Stratix V Network Reference Platform Implementation Considerations
2.6. Establishing Host Communication
After you modify and rebrand the Stratix® V Network Reference Platform to your own Custom Platform, use the tools and utilities in the Custom Platform to establish communication between your FPGA accelerator board and your host application.
- Program your FPGA device with the <your_custom_platform_name>/hardware/<board_name>/base.aocx hardware configuration file and reboot your system.
- Confirm that your operating system recognizes a PCIe® device with your vendor and device IDs.
- For Windows, open the Device Manager
- For Linux, invoke the lspci command
- Run the aocl install <path_to_customplatform> utility command to install the kernel driver on your machine.
- Ensure that you properly set the LD_LIBRARY_PATH environment variable on Linux or the PATH environment variable on Windows.
For more information about the settings for LD_LIBRARY_PATH or PATH, refer to the Setting the Intel® FPGA SDK for OpenCL™ User Environment Variables section of the Intel® FPGA SDK for OpenCL™ Getting Started Guide.
- To instruct the MMD software not to use CvP or flash memory to program the FPGA, perform one of the following tasks :
- To force the MMD to program via the quartus_pgm executable, set the environment variable ACL_PCIE_FORCE_USB_PROGRAMMING to a value of 1.
- To force the MMD to program via your custom programming method, modify the <your_custom_platform_name>/source/host/mmd/acl_pcie_device.cpp file. Trace the appearance of the environment variable ACL_PCIE_FORCE_USB_PROGRAMMING in the source code, and replace the existing instruction with your custom programming method.
- Modify the version_id_test function in the MMD source code in the <your_custom_platform_name>/source/host/mmd/acl_pcie_device.cpp file to exit after reading from the version ID register.
- Remake the MMD software.
- Run the aocl diagnose utility command and confirm the version ID register reads back the ID successfully. You may set the environment variables ACL_HAL_DEBUG and ACL_PCIE_DEBUG to a value of 1 to visualize the result of the diagnostic test on your terminal.
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