Intel® FPGA SDK for OpenCL™: Stratix® V Network Reference Platform Porting Guide
ID
683645
Date
11/06/2017
Public
2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
3.6.3. Floorplan
The Intel® FPGA SDK for OpenCL™ requires all board logic to be constrained along the edges of the FPGA device. This constraint provides a large contiguous space for OpenCL kernel implementation, which generally leads to better circuit performance (that is, Fmax).
The Stratix® V Network Reference Platform floorplan below shows that all board interface logic are along the edges of the device. The logic in the center is the OpenCL kernel. At the bottom of the device are the PCIe® and the two DDR3 cores. The QDR controllers are along the top of the device, and the two UDP stacks are on the right. The Stratix V global clock buffers are all around the middle of the device. This floorplan accommodates access to the global clock buffers by extending the bottom region edges up the left and right sides. This extension allows the placement of reset and other global routing drivers in the bottom region to be near the global clock buffer.
Figure 2. S5_net Floorplan
You can derive a floorplan for any board by following these steps:
- Compile the design without any region constraints.
- Examine the placement location of each of the IP cores in the Chip Planner.
- Apply Logic Lock regions to push the IP cores to the edges of the device.