Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022
Public
Document Table of Contents

1. Introduction to the Intel® Stratix® 10 Hard Processor System Component

Updated for:
Intel® Quartus® Prime Design Suite 21.3
The hard processor system (HPS) component is a wrapper that interfaces logic in your design to the:
  • HPS hard logic
  • Simulation models
  • Bus functional models (BFMs)
  • Software handoff files
The HPS component instantiates the HPS hard logic in your design and enables other soft components to interface with the HPS hard logic. The HPS component has a small footprint in the FPGA fabric, as the component only serves to enable soft logic to hard logic connection in the HPS.

After you connect the soft logic to the HPS, you can use Platform Designer to ensure the following features:

  • Interoperability by adapting Avalon® Memory-Mapped ( Avalon® -MM) interfaces to AXI*
  • Handling of data width mismatches and clock domain transfer crossings

You are able to integrate Intel® FPGA IP, 3rd party IP, and custom IP that you define into the HPS without creating integration logic. This reference manual details the interfaces exposed and configured by the options in the component.

For more information about the HPS system architecture and features, refer to the "Introduction to the Hard Processor" chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.

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