1. Introduction to the Intel® Stratix® 10 Hard Processor System Component
|Intel® Quartus® Prime Design Suite 21.3|
- HPS hard logic
- Simulation models
- Bus functional models (BFMs)
- Software handoff files
After you connect the soft logic to the HPS, you can use Platform Designer to ensure the following features:
- Interoperability by adapting Avalon® Memory-Mapped ( Avalon® -MM) interfaces to AXI*
- Handling of data width mismatches and clock domain transfer crossings
You are able to integrate Intel® FPGA IP, 3rd party IP, and custom IP that you define into the HPS without creating integration logic. This reference manual details the interfaces exposed and configured by the options in the component.
For more information about the HPS system architecture and features, refer to the "Introduction to the Hard Processor" chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.
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