Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

3.1.3.2.2. BFM API Hierarchy Format

For post-fit simulation, you must call the BFM API in your test program with a specific hierarchy. The hierarchy format is:

<DUT>.\<HPS>|fpga_interfaces|<interface> <space>.<BFM>.<API function>

Where:

  • <DUT> is the instance name of the design under test that you instantiated in your test bench . The design under test is the HPS component.
  • <HPS> is the HPS component instance name that you use in your Platform Designer system.
  • <interface> is the instance name of a specific FPGA-to-HPS or HPS-to-FPGA interface. This name can be found in the fpga_interfaces.sv file located in <project directory> / <Platform Designer design name> /synthesis/submodules.
  • <space>—You must insert one space character after the interface instance name.
  • <BFM> is the BFM instance name. To identify the BFM instance name, in <ACDS install> /ip/altera/hps/postfitter_simulation, find the SystemVerilog file corresponding to the interface type that you are using. This SystemVerilog file contains the BFM instance name.

For example, a path for the Lightweight HPS-to-FPGA master interface hierarchy can be formed as follows:

top.dut.\my_hps_component|fpga_interface|hps2fpga_light_weight .h2f_lw_axi_master

Notice the space after hps2fpga_light_weight. Omitting this space can cause simulation failure because the instance name hps2fpga_light_weight , including the space, is the name used in the post-fit simulation model generated by the Intel® Quartus® Prime software.

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