Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.6.2. Advanced

The Advanced tab is divided into two sub-tabs, Advanced IP Placement and Advanced FPGA Placement.

Advanced IP Placement

The Advanced IP Placement tab allows you to be more specific about the placement of each peripheral pin in the HPS dedicated I/O quadrant space. Each location has a pulldown selection menu where you can select which peripheral I/O to be routed to the pin location. Each pulldown menu corresponds to the inputs available to the pinmux at that location. Changes to a dropdown only become effective when the Apply Selections button is pressed. Changes in the Advanced IP Placement tab carry over to the Auto-Place IP tab. The Pin Mux Report and EMAC ptp interface sections are identical to those in the Auto-Place IP tab.

Advanced FPGA Placement

The Advanced FPGA Placement tab allows you to route specific peripherals to the FPGA, if those peripherals were enabled and allocated to the FPGA in the Auto-Place IP tab. Similar options for the SD/MMC, NAND, and TRACE bit-width allow you to specify how wide the interfaces should be when routed to the FPGA. Changes to a dropdown only become effective when the Apply Selections button is pressed. Changes in the Advanced FPGA Placement tab carry over to the Auto-Place IP tab. The Pin Mux Report and EMAC ptp interface sections are identical to those in the Auto-Place IP tab.

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