Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022
Public
Document Table of Contents

2.2.4. DMA Controller Interface

The DMA controller interface allows soft IP in the FPGA fabric to communicate with the DMA controller in the HPS. You can configure up to eight separate interface channels by clicking on the dropdown in the Enabled column for the corresponding channel row. Each DMA peripheral request interface conduit f2h_dma<n> contains the following three signals, where <n> corresponds to a specific request interface enabled in Platform Designer:
  • f2h_dma<n>_req—This signal is used to request burst transfer using the DMA
  • f2h_dma<n>_single—This signal is used to request single word transfer using the DMA
  • f2h_dma<n>_ack—This signal indicates the DMA acknowledgment upon requests from the FPGA
Note: FPGA DMA interfaces 6 and 7 are multiplexed with the EMAC2 I2C DMA interface.

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