Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.2.2.4. FPGA-to-HPS SDRAM AXI* -4 Slave Interface

The FPGA-to-HPS SDRAM interface is a group of three direct connections between the FPGA fabric and the HPS SDRAM Scheduler in the L3 SDRAM Interconnect. For each of the F2SDRAM interfaces, you can select between 32-, 64- or 128-bit data widths using the corresponding enable/data width dropdown. The Ready Latency pipeline dropdowns configure the flexible ready latency pipelining available in the FPGA fabric for each corresponding interface. This can assist with timing closure at the FPGA-to-HPS boundary and is configurable to depths of 0 (none), 1, 2, 3, or 4. The Bridge address width is configurable from 37 bits to 21 bits. Each command channel to the SDRAM controller has an individual clock source from the FPGA fabric. The interface clock is always supplied by the FPGA fabric, with clock crossing occurring on the HPS side of the boundary. The FPGA-to-HPS SDRAM clocks are driven by soft logic in the FPGA fabric.

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