Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022
Public

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3.1.1.1. HPS Conduit Interfaces Connecting to the FPGA

The following tables define the HPS Conduit interfaces that connect to the FPGA.

Table 5.   h2f_warm_reset_handshake

Role Name

Direction

Width

h2f_pending_rst_req_n

Output

1

f2h_pending_rst_ack_n

Input

1

Table 6.  h2f_gp
Role Name Direction Width
h2f_gp_in Input 32
h2f_gp_out Output 32
Table 7.  h2f_mpu_events
Role Name Direction Width
h2f_mpu_eventi Input 1
h2f_mpu_evento Output 1
h2f_mpu_standbywfe Output 4
h2f_mpu_standbywfi Output 4
Table 8.  f2h_dma0 to f2h_dma7
Role Name Direction Width
f2h_dma_req<0-7>_req Input 1
f2h_dma_req<0-7>_single Input 1
f2h_dma_req<0-7>_ack Output 1
Table 9.  h2f_debug_apb_sideband
Role Name Direction Width
h2f_dbg_apb_PCLKEN Input 1
h2f_dbg_apb_DBG_APB_DISABLE Input 1
Table 10.  f2h_stm_hw_events
Role Name Direction Width
f2h_stm_hwevents Input 43
Table 11.  h2f_cti
Role Name Direction Width
h2f_cti_trig_in Input 8
h2f_cti_trig_in_ack Output 8
h2f_cti_trig_out Output 8
h2f_cti_trig_out_ack Input 8
h2f_cti_fpga_clk_en Input 1
Table 12.  h2f_tpiu
Role Name Direction Width
h2f_tpiu_clk_ctrl Input 1
h2f_tpiu_data Output 32