Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022
Public
Document Table of Contents

3.3. FPGA-to-HPS AXI* Slave Interface

The FPGA‑to‑HPS AXI* slave interface, f2h_axi_slave, is connected to a Mentor Graphics® AXI* slave BFM for simulation with an instance name of f2h_axi_slave_inst. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to f2h_axi_clock clock.

Table 20.  Configuration of FPGA-to-HPS AXI* Slave BFM

Parameter

Value

AXI* Address Width

20 - 37

AXI* Read Data Width

128

AXI* Write Data Width

128

AXI* ID Width

4

You control and monitor the AXI* slave BFM by using the BFM API.

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