Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 12/14/2022

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Document Table of Contents FPGA-to-HPS Slave Interface

The FPGA-to-HPS interface is:
  • 128-bit width ACE-Lite compliant slave allowing FPGA masters to issue transactions to the HPS
  • Configurable to be an AXI* -4 compliant slave, using the Interface Specification dropdown
Since the FPGA-to-HPS interface is fixed-width:
  • Enable/Data Width dropdown allows you to choose whether the interface is disabled (unused) or enabled and 128 bits wide.
  • Ready Latency pipeline dropdown configures the flexible ready latency pipelining available in the FPGA fabric. This can assist with timing closure at the FPGA-to-HPS boundary and is configurable to depths of 0 (none), 1, 2, 3, or 4.
  • Bridge address width is configurable from 20 bits to 37 bits, which allows the FPGA fabric to access the majority of the HPS address space. To facilitate masters in the FPGA logic with a smaller address width than the bridge in accessing the HPS address space, you can use the Intel® Address Span Extender component.

For more information, refer to the "Using the Address Span Component Extender" chapter.

When this bridge is enabled, the interfaces f2h_axi_slave, f2h_axi_clock,and f2h_axi_reset are made available.

This interface allows the FPGA to access the majority of the HPS slaves. When configured as an ACE-lite slave, this interface provides a coherent memory interface. Other interface standards in the FPGA fabric, such as connecting to Avalon® Memory Mapped ( Avalon® -MM) interfaces, can be supported through the use of soft logic adapters. The Platform Designer system integration tool automatically generates adapter logic to connect AXI* to Avalon® -MM interfaces.

For more information, refer to Features of the Intel Stratix 10 HPS-FPGA Bridge in the "HPS-FPGA Bridges" chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.