Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

2.6.1. Auto-Place IP

The Auto-Place IP tab contains a list of HPS peripherals that can be enabled and either routed to the HPS I/Os or to the FPGA. You can enable the following types of peripherals:
  • NAND Flash Controller
  • SD/MMC Controller
  • Ethernet Media Access Controller
  • USB 2.0 OTG Controller
  • I2C Controller
  • UART Controller
  • SPI Master
  • SPI Slave
  • CoreSight Debug and Trace

For more information about each of these HPS peripherals, refer to the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.

You can enable one or more instances of each peripheral type by using the dropdown menu next to each peripheral. When enabled, some peripherals also have mode settings specific to their functions. Once you have selected a peripheral, you must click the Apply Selections button in order to enable the selected peripherals. Clicking the Apply Selections button triggers the HPS component to do a best-effort automatic placement of the enabled peripheral signals to the HPS I/Os. This overrides any settings already chosen in the Advanced tab. The results of this placement becomes visible in the I/O Selections section on the right side of the Auto-Place IP tab. Any messages, such as failures to place a peripheral, appears in the message box in the I/O Selections section.

If the NAND, SD/MMC, or TRACE peripherals are enabled, there are further options to specify the desired bit width of the interface routed to the HPS I/Os. If any of the EMACs are enabled, the corresponding Interface and PHY Options dropdowns becomes available to specify the desired EMAC parameters.

The Pin Mux Report section details which physical pins of the device map to each HPS I/O location. In the Emac ptp interface section, there are options to turn on for each EMAC to enable the Precision Time Protocol (ptp) FPGA interface. These options are only applicable when an EMAC is routed to the HPS pins. When enabled, the signals emac<n>_ptp_pps_o, emac<n>_ptp_aux_tx_trig_i, emac<n>_ptp_tstmp_data, emac<n>_ptp_tstmp_en, as well as the emac_ptp_ref_clock clock input interface, are made available. When an EMAC is routed to the FPGA pins, these signals are automatically included in the emac<n> conduit.

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