126.96.36.199. HPS to FPGA User Clocks
Turning on the Enable HPS-to-FPGA User0 clock or Enable HPS-to-FPGA User1 clock option enables one of two available HPS PLL outputs into the FPGA. You can connect a user clock to logic that you instantiate in the FPGA. When you enable a HPS-to-FPGA user clock, you must manually enter its maximum frequency for timing analysis. The Timing Analyzer has no other information about how software running on the HPS configures the phase-locked loop (PLL) outputs. Both user clocks are driven from peripheral PLL.
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