Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 8/05/2021
Public
Document Table of Contents

3.4. HPS-to-FPGA AXI* Master Interface

The HPS-to-FPGA AXI* master interface, h2f_axi_master, is connected to a Mentor Graphics AXI* master BFM for simulation with an instance name of h2f_axi_master_inst. In Platform Designer, you can configure the HPS-to-FPGA interface with the following address, data, and ID widths. The BFM clock input is connected to h2f_axi_clock clock.

Table 21.  Configuration of HPS-to-FPGA AXI* Master BFM

Parameter

Value

AXI* Address Width

32

AXI* Read and Write Data Width

32, 64, or 128

AXI* ID Width

4

You control and monitor the AXI* master BFM by using the BFM API.

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